The present invention relates to a polishing method adapted for the manufacture of a semiconductor device, etc., and a polishing liquid used in the polishing method.
In recent years, researches and developments of various fine processing technologies are being conducted in the field of manufacturing a semiconductor device in accordance with progress in the density and fineness of the semiconductor device. Particularly, a CMP (Chemical Mechanical Polishing) technology is absolutely necessary for flattening the interlayer insulating film, for forming a plug, for forming a buried metal wiring, and for forming a buried element isolation.
Use of the CMP technology is also being tried in the processing of an electrode for a capacitor. Particularly, it is considered very important to establish a method utilizing the CPM technology in the manufacture of DRAM or FRAM of the next era using a perovskite crystal for forming a dielectric film. It should be noted in this connection that it is necessary to select a noble metal or a perovskite type conductive oxide for forming the lower electrode of a capacitor in view of the compatibility of the lower electrode with the dielectric film. However, the noble metal and the perovskite type conductive oxide is chemically stable in general, making it difficult to employ a wet etching or a dry etching for processing the lower electrode of the capacitor. Such being the situation, it is considered very important to establish a method using the CPM technology.
On the other hand, the possibility of processing is increased in the CMP technology because a chemical function and a mechanical function are utilized in good balance in the polishing by the CMP technology.
However, the conventional polishing liquid used in the CMP technology was defective in that the polishing rate was low, leading to a low manufacturing efficiency of the semiconductor device. Also, the conventional polishing liquid was low in the selectivity ratio of the polishing rate relative to the underlying stopper film, making it difficult to obtain an uniform and stable processed configuration over the entire surface region of a single wafer or among different wafers.